A serial interface circuit is known that uses a plurality of channels. For example, in Japanese Patent Application Publication (JP-P2006-302277A), a serial transmission through channels is disclosed. In this conventional example, word synchronization and de-skew (synchronization with a system clock signal) are carried out in different blocks. Inter-channel synchronization is carried out in a byte serial-parallel converter, a phase compensation FIFO or the like in a further back stage of the above block. In the standards of Infiniband and 10 Gbit Ethernet, the number of skip signals subsequent to a comma signal as a header bit sequence is increased or decreased to compensate a clock rate difference between a serial transmitter and a serial receiver.
In such a conventional example, there are the following problems. At first, the word synchronization, the de-skew, the compensation for a rate difference in clock signals, and the inter-channel synchronization are separately performed in different blocks. As a result, a header detection is performed for the word synchronization, and the detected signal is used only for the word synchronization. In order to detect a head portion of data in each of channels for the inter-channel synchronization, it is necessary that another detecting circuit different from a circuit for the header detection is provided to detect the header portion. For this reason, there is the problem that a latency becomes long.
Next, a FIFO circuit which requires many registers is used in the de-skewing circuit, a rate compensating circuit and an inter-channel aligning circuit. Thus, there is the problem that the hardware becomes large.
Moreover, in a serial transmission circuit having a plurality of channels, the circuit is designed under an assumption that, when an error is generated even in one bit, all data are re-transmitted. For this reason, there is the problem that the generation of the error involves a long latency and also a memory for storing the data is required.
In the conjunction with the above description, Japanese Patent Application Publication (JP-P2006-302277A) discloses a receiver of a serial interface. In this conventional example, the receiver of the serial interface is used in a programmable logic device. The receiver of the serial interface includes a word alignment stage that contains at least one block for providing a word aligned output, a de-skew stage that contains at least one block for providing a de-skew output, and a rate matching stage that contains at least one block for providing a rate aligned output. The receiver further includes an embedded protocol decoder stage that contains at least one block for providing a decoded output, a byte serial-parallel converter stage that contains at least one block for providing a parallel output, a byte re-arrangement stage that contains at least one block for providing a re-arranged output, and a phase compensation stage that contains at least one block for providing a phase compensated output. The receiver further includes bypass circuits around the respective stages, and a selector circuit for selecting outputs from the outputs of the stages and the outputs of the bypass circuits. Thus, any one stage among the plurality of stages can be programmably included in the receiver of the serial interface.
Japanese Patent Application Publication (JP-A-Heisei 10-97481) discloses a microcomputer. The conventional microcomputer includes a CPU, a receiving circuit for sequentially receiving serial data supplied from an external circuit, and a header detecting circuit for detecting whether or not a partial data already received by the receiving circuit has a part coincident with a predetermined header. When the partial data is detected to has the part coincident with the predetermined header, an interrupting circuit issues an interrupt to the CPU to perform a predetermined interrupting process corresponding to the header on the following partial data, each time the receiving circuit receives a plurality of partial data following the above partial data after the detection.
Japanese Patent Application Publication (JP-A-Heisei 7-6130) discloses a data transfer circuit. In the conventional data transfer circuit, a synchronous FIFO circuit has a data input, a data output and a control output, and the control output indicates that the synchronous FIFO circuit has data words for transfer. A synchronizing circuit has a control input and a control output, and the control input of the synchronizing circuit is connected to the synchronous FIFO control output. An asynchronous FIFO circuit has a data input, a control input and a data output, and the data input of the asynchronous FIFO circuit is connected to the data output of the synchronous FIFO circuit, and the control input of the asynchronous FIFO circuit is connected to the control output of the synchronizing circuit. An asynchronous data signal, which is supplied from one of asynchronous apparatuses to the data input of the synchronous FIFO circuit, is outputted to the other of the asynchronous apparatuses from the output of the asynchronous FIFO circuit after a transmission delay.
Japanese Patent Application Publication (JP-A-Heisei 2-85950) discloses an inter-bus transfer system. The inter-bus transferring system is provided with a microprocessor, a memory, a direct memory access controller, a serial controller, a plurality of I/O function blocks, and a common bus for connection between the respective units. This inter-bus transfer system is further provided with a local bus that can arbitrarily change a data transfer direction when a data is transferred between the serial controller and the plurality of I/O function blocks, a register file of a first kind to change the data transfer direction between the local bus and the serial controller; and a plurality of register files of a second kind to change the data transfer direction between the local bus and each of the plurality of I/O function blocks.